1. Field of the Invention
The present invention relates to an input/output interfacing circuit implemented in a semiconductor device, etc., and in particular it relates to an input/output interfacing circuit capable of inputting and outputting multiple values by a single signal line.
2. Description of the Related Art
Semiconductor devices such as a memory LSI, microprocessor, etc., are in the progress of high integration and high rate through the development of semiconductor manufacturing technology, wherein the data transfer rate has improved year by year.
In prior arts, in order to improve the data transfer rate, for example, in a memory LSI, a clock synchronizing type memory such as a synchronous DRAM, DDR SDRAM (Double Data Rate SDRAM), Rambus DRAM, etc., where an input/output circuit has improved operation speed has been developed. Also, the data transfer rate has been improved by increasing the number of bits of the input/output data to 16 or 32.
However, there is a limitation to heightening the operation speed of the input/output circuits. Also, an increase in the number of terminals increases the number of pads. Since the pad size depends on the packaging technology, it is difficult to shrink the size as semiconductor elements become finer. As a result, there is an undesirable possibility that the chip size is increased due to an increase in the number of pads. Hereafter, there is a possibility that the chip size is determined based on the number of pads. In a memory LSI, even if the number of address terminals is increased owing to the improvement of the integration level and an increase in the memory capacity, the chip size may be increased as described above.
As a way of improving the data transfer rate without an increase in the number of pads, that is, an increase in the chip size, a multiple value of data or addresses is taken into consideration.
FIG. 1 shows a multi-valued input/output circuit that the inventor has studied. The circuit shown in FIG. 1 is not publicly known.
In this type of multi-valued input/output circuit, a voltage generating unit 1 is formed in a semiconductor device at a transmitter that outputs data, and a plurality of voltage comparing units 2, a reference voltage generating unit 3 and a data restoring unit 4 are formed in a semiconductor device at a receiver that receives data.
The voltage generating unit 1 includes a data restoring unit 1a that decodes two-bit output data D1 and D0, a resistor part 1b that generates four types of voltages V4, V3, V2 and V1 by dividing resistance, and an output part 1c that outputs any one of the voltages V4 through V1 as an output voltage VOUT. The output part 1c is composed of a switch such as a CMOS transmission gate, etc. That is, the voltage generating unit 1 gives four types of output voltages VOUT to a semiconductor device at the receiver in response to the output data D1 and D0.
The respective voltage comparing units 2 compare the output voltages VOUT with the reference voltages VREF3.5, VREF2.5 and VREF1.5, respectively, accept the comparison results in synchronization with a clock signal CLK, and output the results as the input results RSL3, RSL2, and RSL1. The reference voltage generating unit 3 generates three types of reference voltages VREF3.5 through VREF1.5 by dividing the resistance. Herein, the reference voltage VREF3.5 is set between voltages V3 and V4, the reference voltage VREF2.5 is set between voltages V2 and V3, and the reference voltage VREF1.5 is set between voltages V1 and V2. That is, the figures at the end of these voltages show the relative values of voltages.
The data restoring units 4 receive the input results RSL3 through RSL1 and make any one of the input data IND3 through IND0 into a high level in accordance with the logic value of the output data D1 and D0.
FIG. 2 shows the detail of the voltage comparing unit 2.
The voltage comparing unit 2 includes a differential amplifier 5, a latching circuit 6, and an output circuit 7. The differential amplifier 5 has a current mirror circuit and changes the output node to a high level or low level in accordance with the output voltage VOUT and reference voltages VREF3.5 (or VREF2.5, VREF1.5). The latching circuit 6 accepts an output from the differential amplifier 5 in synchronization with a rise edge of a clock signal CLK. The output circuit 7 outputs data, which are latched by the latching circuit 6, as the input results RSL3 (or RSL2, RSL1).
FIG. 3 shows the detail of the data restoring unit 4.
In the data restoring unit 4, inverted logic of the input result RSL3 is outputted as input data IND3, inverted logic of the input result RSL2 is outputted as input data IND2 when the input result RSL3 is at a high level, and inverted logic of the input result RSL1 is outputted as input data IND1 when the input result RSL2 is at a high level, and the logic, which is the same as the input result RSL1, is outputted as input data IND0. As a result, for example, when both output data D1 and D0 are at a high level (“3” in the binary code), only the input data IND3 is made into a high level, and when the output data D1 and D0 are in a low level and high level (“1” in the binary code), respectively, only the input data IND1 is made into a high level.
As shown above, in the transmitter, any one of the voltages V4 through V1 divided in response to the output data D1 and D0 is selected and outputted as an output voltage VOUT. In the receiver, by obtaining the logic value corresponding to the output voltage VOUT, a multiple value (in this case, 2 bits) are transmitted and received.
However, the voltage generator unit 1 of the transmitter selects any one of a plurality of voltages V4 through V1, which are obtained by dividing the resistance, by a switch such as a CMOS transmission gate, etc., in response to the output data D1 and D0. The difference in voltage corresponding to the logic value is small because the voltages are generated by dividing the resistance. Therefore, it was difficult to change the output voltage VOUT to a high rate when switching the CMOS transmission gate, etc. Since the difference in voltage corresponding to the logic value is small, only two-bit of data could be made into a multiple value.
In addition, the voltage range in which the differential amplifier 5 effectively operates is predetermined in the receiver, which makes it difficult to actuate the differential amplifier 5 in all the ranges of the output voltages VOUT. As a result, the differential amplifiers 5 of the voltage comparing units 2 shown in FIG. 2 have to be designed so as to optimally operate in correspondence with the received output voltage VOUT, respectively.